Electronics

The task of the front end electronics is to provide timing and pulse height information for signals produced by decay positrons in the two layers of scintillating tiles. As mentioned previously, we will take all data using waveform digitizers connected to every channel. In addition to the basic experimental measurement, both pulse height and timing information will be used to suppress and correct for pulse pileup, which we expect to be one of the experiment's largest systematic errors. Our design is based in part on our experience in the 2 experiment, where information about the pulse shapes has proven a powerful tool in suppressing backgrounds and diagnosing pileup from decay electrons spaced closely in time. For detecting pulse pileup, the waveform need not even reveal a noticeable cleft between two peaks. Often, the increased width of the pulse is sufficient to identify it as coming from two decay positrons.

Figure 8 illustrates what the waveform digitizer records for typical MIP pulses in BC404 scintillator as viewed by Hamamatsu R6427 photomultiplier tubes in the 2 experiment. We have developed analysis routines (see below) which extract the time and energy from these records without introducing bias due to shifting baseline, or two-pulse pileup. This is not possible using leading edge discriminators and conventional time-to-digital converters.

Figure: An example of two nearby hits in plastic scintillators in the 2 experiment as sampled by a 400 MHz waveform digitizer. This set of sample has been selected purposely to illustrate the power of the waveform digitizer approach. It is evident that a normal discriminator / multi-hit TDC approach would have a problem even with these well-separated pulses due to the fact that the second pulse rides on the tail of the first.

The task we address is a demanding one. We require that our system be able to read out 360 channels of phototube signals, one signal from each of the two layers of 180 tiles. The signals from front and back sections of each tile will sit on the same analog line, with the back signal delayed by 40 ns. To keep the beamtime required to a minimum, front end acquisition and readout to tape will proceed in parallel. Some assumptions:

1.

9 decay positrons are detected in each measuring cycle

2.

Each pulse is sampled at 2 ns intervals for 40 ns with an 8-bit flash ADC

3.

A 16 bit time word will accompany each set of 6 samples.

4.

Each accumulation/measuring cycle lasts for 12 $\mu$s.

With overhead, this results in 50 MBytes per second which presents no particular challenge for the front end digitizers and the memory to which their data is written, but will put a tremendous burden on the data acquisition system.

Block diagrams of the waveform digitizer (WFD) are shown in figures 9 and 10. An analog waveform from the PMT is sent to an 8-bit 500 MHz flash ADC. Every six bytes of flash ADC information (12 ns) are accompanied by a 16 bit time word. The six ADC samples and two bytes of time information are assembled into one 64-bit word by an on-board ASIC, much like the one used on the waveform digitizers built for the 2 experiment. The time word will be latched from a counter on the ASIC, which will be driven, in turn, by the same clock which strobes the flash ADC. The 64 bits of time and ADC sample information will be written to the FIFO memory at 500/6 MHz.

Figure 9: Block diagram for a 500 MHz Wave Form Digitizer (WFD) with First in First Out (FIFO) memory for continuous real-time data acquisition.

Figure 10: Layout diagram for the 500 MHz WFD on a 6U size VME card.

In normal operation, the ASIC will perform zero suppression on the data, writing blocks of data to memory only when a logic level produced by the front end comparator indicates that the analog signal has exceeded some programmable threshold. The FIFO we have selected, the IDT72, can be written to and read from at the same time at 100 MHz. 36 ns of sampling would imply 24 bytes written per pulse, 18 of flash ADC information and 6 of time, or an overall data rate (for all detectors) of 50 Mbytes per second, which will require the use of VME-64 or VME-320 bus architecture, if significant numbers of boards are located in a single crate.

Various control signals will be required to operate the µLan WFD. The ASIC will write data to memory only when enabled by a front panel start signal and will cease to write data when it receives a front panel STOP. A VETO input will disable the writing of data without stopping the clock. A RESET input will zero the clock and memory counter.

A Control/Status register will be used to control and monitor the board. The control register will include software emulation of front panel hardware such as START and STOP, so that the board can be operated by a computer alone, as well as bits to set the threshold for the front-end comparator, or to activate or disable zero suppression. The status register will describe the state of the board, including error conditions, the number of data acquisition cycles since RESET, and most importantly, the location of the data pointer in memory.

The µLan WFD will be checked for time and gain stability using a variety of techniques we developed for the 2 experiment, both on the lab bench and in the experimental hall itself. Of particular concern are effects which vary with the time since injection and can therefore change directly our exponential timing curve. In addition, we must demonstrate that the two-pulse resolving power within our nominal 10 ns deadtime, that is how often we know that there are two pulses overlapping even if we can't say much more than that, will be sufficient to keep the systematic error from pileup at a manageable level.

A word should also be said about the time standard for the muon lifetime experiment. The clock system required would bear a strong resemblance to that for 2. The clock signals required by the WFDs would be generated by a precision oscillator such as the PTS 310. In order to guarantee its long-term stability, the PTS would be synchronized to an external frequency standard such as GPS. Unlike 2, which requires only the measurement of frequency ratios, a measurement of the lifetime requires an absolute frequency measurement. A frequency monitoring system for the experiment's clock is therefore essential. It is not difficult to obtain absolute clock precision below 10^-7.