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Re: Progress on Compressors
Dear Fred,
Concerning situation (a)
-------------------------------
The transfer rate from the compressor is high.: 200 ns per 32 bits in
parallel=20MBytes/s What is the speed of your processor reading out the SIS FIFO?
Is it higher than 20MBytes/s?
1)If so, your are right. You could end the readout before the transfer to the SIS
FIFO is completed. But don’t forget that in this mode the data flow is steady at
20 MB/s. Anyway if it occurs then we should think on your suggestion b)
2) If not so, then no problem the SIS FIFO will be totally loaded before you
empty it.
Concerning situation (b)
-------------------------------
If you read only a fraction of the data, how do you know that you have to read the
SIS FIFO once more? Nobody is telling that? How do you now that you have to align
back this remaining part?
If one runs with 2 cards, all the FPGA are spited in about two equal parts. The
maximum volume of the 20 FIFOS belonging to the FPGAs housed in one crate is 512
*20 words of 32 bits = 40 kBytes. The size of the SIS FIFO is 128kBytes. So the
SIS FIFO may contain two events.
If scenario (b) needs to be applied (the DAQ processor is the fastest), I suggest
reading the first part and reading the remaining during the next event since the
SIS FIFO can house both events. The separation between both events can be found by
checking the FPGA number evolution. When the FPGA number is lower than the
previous one, then a new data flow is beginning
.
Notes:
-------
In the present mode we always have a macro dead time during the data transfers.
With the OR of two inhibit signals: a) one internal generated in the controller
during the transfer to the SIS FIFO and b) one external coming from the DAQ. When
this level is removed the compressors automatically restart their job filling the
compressor FIFOs. It only needs a TIMECLEAR signal before the end of the inhibit
period for resetting the time to zero.
If other modules than the compressors tell that one should end the event and start
reading, this will be identified by the beginning of the INHIBIT level (the front
edge) sent to the compressor’s controller. Then the data transfer to the SISFIFO
will be initiated and an internal INHIBIT generated up to the end of the transfer
to the SIS FIFO.
A real macro dead time free mode is possible if one uses the previous compressor
mode but then the DAQ must poll or be interrupted at the half full of the SIS FIFO
sending a TIMECLEAR signal at every readout and an INHIBIT level generated only
when the DAQ is stopped or overloaded
The time for filling uniformly 20 FPGAs (if no oscillations) is 34 ms for 50kHz
muon stops. The clock round over time is 503 ms (50MHz clock). Time precision = 30
ns.
Best regards,
René
Fred Gray a écrit :
> > We are presently running in the new proposed mode: FIFO compressors
> > being filled without transfer to the SIS FIFO until one of the
> > compressors is full. Then the acquisition is stopped and the content of
> > each compressor is send to the VME SIS FIFO. This works ... but still
> > some details to be arranged. I remind you that the transfer time from
> > compressors to SIS FIFO is of 512*0.2 us = 100 us per FPGA (64 wires).
> > Consequently if all FPGA are uniformly filled during acquisition and if
> > one have two crates working independently housing 10 compressors each (=
> > 20 FPGAs) the filling time will be of 2 ms maximum but will already be
> > started before the DAQ starts the SIS readout. Unfortunately the
> > electronician working on this project had to go in surgery; he will be
> > back by the end of April...
>
> Dear Rene,
>
> Thanks for this update. I'm afraid that I missed the discussion of this
> topic: what was the motivation for this change?
>
> >From the DAQ perspective, I guess there are two approaches to dealing with
> this new format:
>
> (a) During deadtime between events, read out the compressor data from
> the SIS FIFO. Since data will be continually arriving in the SIS FIFO
> during this time, we can't assume that the end of valid data in the SIS FIFO
> corresponds to the end of the compressor data for the event. Consequently,
> there needs to be some unambiguous end-of-data marker in the stream sent to
> the SIS FIFO. I'm not sufficiently familiar with the compressors to
> know whether not this marker already exists. This option will lead to a
> deadtime of a few ms per event, and events will typically be about 40 ms
> long (scale set by the TDC400). This deadtime is therefore on the order
> of 10%, which may or may not be considered acceptable.
>
> OR
>
> (b) Go ahead and start the next event before the transfer to the SIS FIFO
> has completed and then read out the SIS FIFO during this next event.
> The resulting data would be placed one stage back in the pipeline, so it would
> still be aligned with the data from other modules from the same event.
> This approach is deadtime-free. However, there is a possibility that the DAQ
> will occasionally fall behind and not complete the readout before the end of
> the next event. In this case, the SIS FIFO would contain data from two
> different events. Consequently, an end-of-data marker would be necessary
> in this case as well. Alternatively, a signal could be generated by the
> DAQ to inhibit transfers to the SIS FIFO if that would be easier for you
> to support.
>
> Also, I assume that you have the ability to force a transfer to the SIS FIFO
> at the end of any DAQ event, not only when one of the compressors fills up
> (i.e. when the event size will be limited by the TDC400, or by the CAEN TDC,
> or by a timeout)?
>
> Thanks,
>
> -- Fred
>
> -- Fred Gray / Visiting Postdoctoral Researcher --
> -- Department of Physics / University of California, Berkeley --
> -- fegray@uclink.berkeley.edu / phone 510-642-4057 / fax 510-642-9811 --
--
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René PRIEELS Universite Catholique de Louvain
email: prieels@fynu.ucl.ac.be Departement de Physique / FYNU
Tel : ++ 32 (0)10 / 47 32 09 Chemin du cyclotron, 2
Fax : ++ 32 (0)10 / 45 21 83 B-1348 Louvain-la-Neuve - BELGIUM
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