Re: Progress on Compressors

[Fred Gray <fegray@socrates.berkeley.edu>]

> We are presently running in the new proposed mode: FIFO compressors
> being filled without transfer to the SIS FIFO until one of the
> compressors is full. Then the acquisition is stopped and the content of
> each compressor is send to the VME SIS FIFO. This works ... but still
> some details to be arranged. I remind you that the transfer time from
> compressors to SIS FIFO is of 512*0.2 us = 100 us per FPGA (64 wires).
> Consequently if all FPGA are uniformly filled during acquisition and if
> one have two crates working independently housing 10 compressors each (=
> 20 FPGAs) the filling time will be of 2 ms maximum but will already be
> started before the DAQ starts the SIS readout.  Unfortunately the
> electronician working on this project had to go in surgery; he will be
> back by the end of April...

Dear Rene,

Thanks for this update.  I'm afraid that I missed the discussion of this 
topic: what was the motivation for this change?

>From the DAQ perspective, I guess there are two approaches to dealing with
this new format:

(a) During deadtime between events, read out the compressor data from
the SIS FIFO.  Since data will be continually arriving in the SIS FIFO
during this time, we can't assume that the end of valid data in the SIS FIFO
corresponds to the end of the compressor data for the event.  Consequently,
there needs to be some unambiguous end-of-data marker in the stream sent to
the SIS FIFO.  I'm not sufficiently familiar with the compressors to
know whether not this marker already exists.  This option will lead to a
deadtime of a few ms per event, and events will typically be about 40 ms
long (scale set by the TDC400).  This deadtime is therefore on the order
of 10%, which may or may not be considered acceptable.

OR

(b) Go ahead and start the next event before the transfer to the SIS FIFO
has completed and then read out the SIS FIFO during this next event.
The resulting data would be placed one stage back in the pipeline, so it would
still be aligned with the data from other modules from the same event.
This approach is deadtime-free.  However, there is a possibility that the DAQ
will occasionally fall behind and not complete the readout before the end of
the next event.  In this case, the SIS FIFO would contain data from two
different events.  Consequently, an end-of-data marker would be necessary
in this case as well.  Alternatively, a signal could be generated by the
DAQ to inhibit transfers to the SIS FIFO if that would be easier for you
to support.

Also, I assume that you have the ability to force a transfer to the SIS FIFO
at the end of any DAQ event, not only when one of the compressors fills up
(i.e. when the event size will be limited by the TDC400, or by the CAEN TDC,
or by a timeout)?

Thanks,

-- Fred

-- Fred Gray / Visiting Postdoctoral Researcher                       --
-- Department of Physics / University of California, Berkeley         --
-- fegray@uclink.berkeley.edu / phone 510-642-4057 / fax 510-642-9811 --