Progress on Compressors

[René Prieels <R.Prieels@fynu.ucl.ac.be>]

Dear Peter

Progress on compressors.

We are presently running in the new proposed mode: FIFO compressors
being filled without transfer to the SIS FIFO until one of the
compressors is full. Then the acquisition is stopped and the content of
each compressor is send to the VME SIS FIFO. This works ... but still
some details to be arranged. I remind you that the transfer time from
compressors to SIS FIFO is of 512*0.2 us = 100 us per FPGA (64 wires).
Consequently if all FPGA are uniformly filled during acquisition and if
one have two crates working independently housing 10 compressors each (=
20 FPGAs) the filling time will be of 2 ms maximum but will already be
started before the DAQ starts the SIS readout.  Unfortunately the
electronician working on this project had to go in surgery; he will be
back by the end of April...

Finally, for housing the compressors, we also had to come back to an old
designed VME crate with jumpers ... because our fast clock could not
pass correctly trough the new VME bus and could not feed correctly all
the compressors.
So I plan to take an old VME crate from Louvain to PSI  next time.

Best regards,
René


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 René PRIEELS                       Universite Catholique de Louvain
 email: prieels@fynu.ucl.ac.be      Departement de Physique / FYNU
 Tel  : ++ 32 (0)10 / 47 32 09      Chemin du cyclotron, 2
 Fax  : ++ 32 (0)10 / 45 21 83      B-1348 Louvain-la-Neuve - BELGIUM
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