Re: CAEN v767 external clock limitations (fwd)

[Tom Banks <tbanks@socrates.Berkeley.EDU>]

I was wrong--Luisa Vivolo is the PIVC contact.  Here is the CAEN message I
received early in February when I was first investigating the clock
effects in Berkeley.


---------- Forwarded message ----------
Date: Wed, 5 Feb 2003 10:14:53 +0100
From: Carlo Tintori <c.tintori@caen.it>
To: tbanks@socrates.Berkeley.EDU
Cc: Nicola Paoli <n.paoli@caen.it>, Guido Esposito <g.esposito@caen.it>
Subject: Re: CAEN v767 external clock limitations

Dear Tom,
you are right, the external clock specification on the manual is not
correct; when you read "minimum widht", actually it is the "typical period".
Anyway, the limit of 45MHz indicated on the manual takes into account
temperature, power supply, speed grade of the components, etc... and it has
to be considered the worst case. I belive that you cun run up to 50MHz but
you must take care of the duty cycle which should be very close to 50%
otherwise the DLL of the TDC chips will not lock. Just try.
Do not hesitate to contact me again whether you need more help.

    Regards,

        Carlo Tintori

_____________________________________________
Ing. Carlo Tintori
R&D Division - CAEN SpA, Via Vetraia 11
55049 VIAREGGIO - ITALY - URL: http://www.caen.it
Tel. +39 0584 388 398, Fax  +39 0584 388 959


----- Original Message -----
From: "Nicola Paoli" <n.paoli@caen.it>
To: "Carlo Tintori" <c.tintori@caen.it>
Sent: Wednesday, February 05, 2003 8:28 AM
Subject: Fw: CAEN v767 external clock limitations



----- Original Message -----
From: "Tom Banks" <tbanks@socrates.Berkeley.EDU>
To: <info.nuclear@caen.it>
Sent: Tuesday, February 04, 2003 9:17 PM
Subject: CAEN v767 external clock limitations


>
> Dear Sir or Madam,
>
> I am a member of the MuCap experiment, which is being conducted at the
> Paul Scherrer Institut in Switzerland.  We are currently using 3 CAEN
> v767s in our data acquistion system.  As it turns out, we recently
> discovered that we likely overclocked the v767s during some recent test
> runs--we were using a 50 MHz external clock.  Consequently, we are
> currently rethinking how to best operate the v767s, while obeying the
> published specifications.
>
> Now, in the v767 manual, sections 2.4 and 5.5 specify the following
> external clock requirements:
>
> (1) the external clock cannot exceed 45 MHz
> (2) the minimum width of the active part of the external clock
> signal cannot be less than 25 ns.
>
> My question is this: Are these 2 requirements correct?  They appear to be
> inconsistent with one another.  Even with a 40 MHz external clock (25 ns
> period), it seems as though it would be impossible to satisfy requirement
> #2 above.  Can you give us some idea of how to best operate within these
> specified parameters?
>
> Thank you for your time,
> Tom Banks
>
> -----------------------------------------
> Thomas Banks
> Graduate Student Researcher
> UC Berkeley Physics
> Berkeley, CA
> U.S.A.
>
> work phone:  510.642.4966
>     e-mail:  tbanks@socrates.berkeley.edu
> -----------------------------------------
>
>
>
>
>