Re: Berkeley FADC board

[Frederick Gray <fegray@berkeley.edu>]

On Sun, Dec 18, 2005 at 01:30:52PM +0100, Peter Winter wrote:
> Fred,
> 
> I'm here right now, Peter might show up soon.
> I'm waiting for your instructions.

Great!   The current status is that the board sends FADC data that appears
valid for a minute or two after being power cycled, but then after that it
only sends start and stop packets at the beginning/end of each block,
and nothing else.

I have a new firmware version that I would like to load onto the
board.  It does two things:
 (a) fixes a potentially relevant bug that I just found, which may or 
     may not explain this problem, and 
 (b) puts a signal on test point TP2 that should indicate
     whether the problem is in the backend or the frontend FPGA.

So: please connect the board so that I can download firmware to it.
Bernhard had this set up a few hours ago, so the parts should be around
somewhere.  It needs power and a JTAG connection to dolphin's parallel
port through my highly amateur JTAG cable.  (As an alternative, if you are an 
expert WFD programmer now and want to do the download yourself, the
firmware is /tmp/fadc1.mcs on dolphin.)

Thanks,

-- Fred

-- Fred Gray / Visiting Postdoctoral Researcher                 --
-- Department of Physics / University of California, Berkeley   --
-- fegray@berkeley.edu / phone 510-642-2438 / fax 510-642-9811  --