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Re: FADC & DEMON
Dear Fred,
Good and bad news.
We were puzzled by a short between VCC and AGRND in the FPGAs!!
We discovered today a mistake in the PCB layout concerning the FADC
In the CAO program used by our electronician, the copper panel under
the FADC needed for heat release was draw to to big and consequently
the surrounding pins are overlapping it by less than one mm.
This induces a short between all pins of the FADCs. The PCB need to be
redone!
But good work and functioning test can still be done on the present
prototype card without the FADCs.
So I will sen you tomorrow the prototype card without the two FADCs but
all the other potential functionalities.
You can generate any kind of data in the front end FPGA and see how
fast it travels through the whole and and what kind of algorithm can be
used.
You may also check the analogue input side. We decide to solder one
entry as single ended signal with a LEMO connector, and the second one
as a differential input.
Here the PCB layout will be modified and reordered as soon as you give
us a green line if no other mis-functioning is discovered from your
tests. We can reorder in July and get the PCBs back in August.
Soldering the components on one board takes only one day.
Best regards
Rene
Le 28-juin-05, à 00:37, Frederick Gray a écrit :
>> We succeeded by configuring both FPGAs with your simple program.
>
> Excellent! Looking forward to having a board to experiment with,
>
> -- Fred
>
> -- Fred Gray / Visiting Postdoctoral Researcher --
> -- Department of Physics / University of California, Berkeley --
> -- fegray@berkeley.edu / phone 510-642-2438 / fax 510-642-9811 --
>
>
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René PRIEELS Universite Catholique
de Louvain
email: R.Prieels@fynu.ucl.ac.be Departement de Physique / FYNU
Tel : ++ 32 (0)10 / 47 32 09 Chemin du cyclotron, 2
Fax : ++ 32 (0)10 / 45 21 83 B-1348 Louvain-la-Neuve -
BELGIUM
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