ispLEVER 3.0.27.16.03_Starter Fitter Report File
Copyright(C), 1992-2001, Lattice Semiconductor Corporation
All Rights Reserved
Project_Summary
Project Name : and0 Project Path : C:\pkammel\mucap\lb500test\aug03 Project Fitted on : Thu Aug 28 00:15:31 2003 Device : LVE5256_144F Package : 256 GLB Input Mux Size : 40 Available Blocks : 8 Speed : -165 Part Number : ispLSI5256VE-165LF256 Source Format : Schematic_Verilog_HDL Project 'and0' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.02 secs Partition Time 0.01 secs Place Time 0.00 secs Route Time 0.00 secs Total Fit Time 00:00:01 Design_Summary
Total Input Pins 0 Total Logic Functions 1 Total Output Pins 1 Total Bidir I/O Pins 0 Total Buried Nodes 0 Total Flip-Flops 0 Total D Flip-Flops 0 Total Latches 0 Total Product Terms 1 Total Reserved Pins 0 Total Locked Pins 0 Total Locked Nodes 0 Total Unique Output Enables 0 Total Unique Clocks 0 Total Unique Clock Enables 0 Total Unique Resets 0 Total Unique Presets 0 Device_Resource_Summary
Total Available Used Available Utilization ---------------------------------------------------------------------- Dedicated Pins Clock/Clock Enable Pins 2 0 2 --> 0 Enable Pins 2 0 2 --> 0 Reset Pins 1 0 1 --> 0 I/O / Clock Pins 2 0 2 --> 0 I/O Pins 142 1 141 --> 0 Logic Functions 400 1 399 --> 0 Input Registers 144 0 144 --> 0 Unusable Macrocells .. 0 .. --> .. GLB Inputs 544 0 544 --> 0 Logical Product Terms 1280 0 1280 --> 0 Occupied GLBs 8 1 7 --> 12 Occupied Macrocells 256 1 255 --> 0 Two Function Macrocells .. 0 .. --> .. One Function Macrocells .. 1 .. --> .. Zero Function Macrocells .. 0 .. --> .. Occupied Product Terms 1304 0 1304 --> 0 Control Product Terms: Global Product Term Enables 4 0 4 --> 0 GLB Clock/Clock Enables 8 0 8 --> 0 GLB Resets 8 0 8 --> 0 Macrocell Clocks 256 0 256 --> 0 Macrocell Clock Enables 1280 0 1280 --> 0 Macrocell Enables 256 0 256 --> 0 Macrocell Resets 256 0 256 --> 0 Macrocell Presets 256 0 256 --> 0 Global Routing Pool 400 0 400 --> 0 GRP from IFB .. 0 .. --> .. (from input signals) .. 0 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 0 .. --> .. GRP from MFB .. 0 .. --> .. ---------------------------------------------------------------------- <Note> 1 : IFB is I/O feedback. <Note> 2 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT I/O Input Macrocells Macrocells Logic clusters Fanin Pins Regs Used Unusable available PTs used ------------------------------------------------------------------------------ Maximum GLB 68 *(1) 16 -- -- 32 160 32 ============================================================================== GLB A 0 0/18 0 0 0 32 0 0 GLB B 0 0/18 0 0 0 32 0 0 GLB C 0 0/18 0 0 0 32 0 0 GLB D 0 0/18 0 0 0 32 0 0 ------------------------------------------------------------------------------ GLB E 0 1/18 0 1 0 31 0 1 GLB F 0 0/18 0 0 0 32 0 0 GLB G 0 0/18 0 0 0 32 0 0 GLB H 0 0/18 0 0 0 32 0 0 ------------------------------------------------------------------------------ <Note> 1 : For pLSI5KVE devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Reset | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 32 32 32 32 32 ============================================================================== GLB A 0 0 0 0 0 0 0 GLB B 0 0 0 0 0 0 0 GLB C 0 0 0 0 0 0 0 GLB D 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ GLB E 0 0 0 0 0 0 0 GLB F 0 0 0 0 0 0 0 GLB G 0 0 0 0 0 0 0 GLB H 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For pLSI5KVE devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : No Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : Yes Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : Speed D/T Synthesis : No XOR Synthesis : Yes Max. P-Term for Collapsing : 35 Max. P-Term for Splitting : 35 Max Symbols : 32 @Utilization_options Max. % of Macrocells used : 100 @TOE_AS_IO Off @Usercode (HEX) @IO_Types Default = LVCMOS25 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_UP (2) @Fast_Bypass Default = None (2) @Input_Registers Default = None (2) Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. Pinout_Listing
| Pin |GLB |Assigned| | Signal| Pin No| Type |Pad |Pin | I/O Type | Type | Signal name ------------------------------------------------------------------- A1 | I_O | G2 | | | | A2 | I_O | G18| | | | A3 | I_O | G20| | | | A4 | I_O | G21| | | | A5 | I_O | G26| | | | A6 | I_O | G28| | | | A7 |CLK_CE0| | | | | A8 | I_O | F4 | | | | A9 | I_O | F5 | | | | A10 | I_O | F12| | | | A11 |I_O/CLK| F16| | | | A12 | I_O | F21| | | | A13 | I_O | F22| | | | A14 | I_O | F28| | | | A15 | I_O | E4 | | | | A16 | I_O | E8 | | | | B1 | I_O | H30| | | | B2 | I_O | G4 | | | | B3 | I_O | G5 | | | | B4 | I_O | G12| | | | B5 | I_O | G14| | | | B6 | I_O | G22| | | | B7 | I_O | G30| | | | B8 |CLK_CE1| | | | | B9 | I_O | F8 | | | | B10 | I_O | F14| | | | B11 | I_O | F18| | | | B12 | I_O | F24| | | | B13 |I_O/CLK| E0 | | | | B14 | I_O | E2 | | | | B15 | I_O | E5 | | | | B16 | I_O | E14| | | | C1 | I_O | H24| | | | C2 | I_O | G6 | | | | C3 | I_O | G8 | | | | C4 | I_O | G10| | | | C5 | I_O | G16| | | | C6 | I_O | G24| | | | C7 | I_O | F0 | | | | C8 | I_O | F2 | | | | C9 | I_O | F6 | | | | C10 | I_O | F10| | | | C11 | I_O | F20| | | | C12 | I_O | F26| | | | C13 | I_O | F30| | | | C14 | NC | | | | | C15 | I_O | E6 | | | | C16 | I_O | E16| | | | D1 | I_O | H21| | | | D2 | I_O | G0 | | | | D3 | I_O | H28| | | | D4 | VCC | | | | | D5 | GND | | | | | D6 | VCC | | | | | D7 | GND | | | | | D8 | GND | | | | | D9 | VCC | | | | | D10 | GND | | | | | D11 | VCC | | | | | D12 | GND | | | | | D13 | GND | | | | | D14 | I_O | E10| | | | D15 | I_O | E12| | | | D16 | I_O | E18| | | | E1 | I_O | H18| | | | E2 | I_O | H26| | | | E3 | I_O | H22| | | | E4 | GND | | | | | E5 | NC | | | | | E6 | NC | | | | | E7 | NC | | | | | E8 | NC | | | | | E9 | NC | | | | | E10 | NC | | | | | E11 | NC | | | | | E12 | NC | | | | | E13 | VCC | | | | | E14 | I_O | E22| | | | E15 | NC | | | | | E16 | I_O | E20| | | | F1 | I_O | H16| | | | F2 | I_O | H20| | | | F3 | I_O | H12| | | | F4 | VCC | | | | | F5 | NC | | | | | F6 | NC | | | | | F7 | NC | | | | | F8 | NC | | | | | F9 | NC | | | | | F10 | NC | | | | | F11 | NC | | | | | F12 | NC | | | | | F13 | GND | | | | | F14 | I_O | E28| | | | F15 | I_O | E21| | | | F16 | I_O | E24| | | | G1 | I_O | H5 | | | | G2 | I_O | H14| | | | G3 | I_O | H6 | | | | G4 | GND | | | | | G5 | NC | | | | | G6 | NC | | | | | G7 | VCC | | | | | G8 | GND | | | | | G9 | GND | | | | | G10 | VCC | | | | | G11 | NC | | | | | G12 | NC | | | | | G13 | VCC | | | | | G14 | TDO | | | | | G15 | I_O | E26| | | | G16 | I_O | E30| |LVCMOS25 | Output|q H1 | I_O | H4 | | | | H2 | I_O | H10| | | | H3 | I_O | H8 | | | | H4 | VCC | | | | | H5 | NC | | | | | H6 | NC | | | | | H7 | GND | | | | | H8 | VCC | | | | | H9 | VCC | | | | | H10 | GND | | | | | H11 | NC | | | | | H12 | NC | | | | | H13 | GND | | | | | H14 |RESETB | | | | | H15 |VCCIO | | | | | H16 | I_O | D30| | | | J1 | TMS | | | | | J2 | I_O | H2 | | | | J3 | I_O | H0 | | | | J4 | GND | | | | | J5 | NC | | | | | J6 | NC | | | | | J7 | GND | | | | | J8 | VCC | | | | | J9 | VCC | | | | | J10 | GND | | | | | J11 | NC | | | | | J12 | NC | | | | | J13 | GND | | | | | J14 | I_O | D24| | | | J15 | I_O | D26| | | | J16 | I_O | D28| | | | K1 | TOE | A0 | | | | K2 | TCK | | | | | K3 | TDI | | | | | K4 | VCC | | | | | K5 | NC | | | | | K6 | NC | | | | | K7 | VCC | | | | | K8 | GND | | | | | K9 | GND | | | | | K10 | VCC | | | | | K11 | NC | | | | | K12 | NC | | | | | K13 | VCC | | | | | K14 | I_O | D20| | | | K15 | I_O | D21| | | | K16 | I_O | D22| | | | L1 | I_O | A4 | | | | L2 | I_O | A2 | | | | L3 | I_O | A5 | | | | L4 | GND | | | | | L5 | NC | | | | | L6 | NC | | | | | L7 | NC | | | | | L8 | NC | | | | | L9 | NC | | | | | L10 | NC | | | | | L11 | NC | | | | | L12 | NC | | | | | L13 | GND | | | | | L14 | I_O | D14| | | | L15 | I_O | D16| | | | L16 | I_O | D18| | | | M1 | I_O | A6 | | | | M2 | I_O | A8 | | | | M3 | I_O | A10| | | | M4 | VCC | | | | | M5 | NC | | | | | M6 | NC | | | | | M7 | NC | | | | | M8 | NC | | | | | M9 | NC | | | | | M10 | NC | | | | | M11 | NC | | | | | M12 | NC | | | | | M13 | GND | | | | | M14 | I_O | D6 | | | | M15 | I_O | D10| | | | M16 | I_O | D12| | | | N1 | I_O | A12| | | | N2 | I_O | A16| | | | N3 | I_O | A14| | | | N4 | GND | | | | | N5 | GND | | | | | N6 | VCC | | | | | N7 | GND | | | | | N8 | GND | | | | | N9 | VCC | | | | | N10 | GND | | | | | N11 | VCC | | | | | N12 | GND | | | | | N13 | VCC | | | | | N14 | I_O | D5 | | | | N15 | I_O | D4 | | | | N16 | I_O | D8 | | | | P1 | I_O | A20| | | | P2 | I_O | A18| | | | P3 | I_O | A26| | | | P4 | I_O | A30| | | | P5 | I_O | B4 | | | | P6 | I_O | B16| | | | P7 | I_O | B24| | | | P8 | I_O | B22| | | | P9 | GOE0 | | | | | P10 | GOE1 | | | | | P11 | I_O | C10| | | | P12 | I_O | C12| | | | P13 | I_O | C24| | | | P14 | I_O | C22| | | | P15 | I_O | C30| | | | P16 | I_O | D2 | | | | R1 | I_O | A21| | | | R2 | I_O | A22| | | | R3 | I_O | A24| | | | R4 | I_O | B0 | | | | R5 | I_O | B2 | | | | R6 | I_O | B6 | | | | R7 | I_O | B14| | | | R8 | I_O | B21| | | | R9 | I_O | B30| | | | R10 | I_O | C0 | | | | R11 | I_O | C14| | | | R12 | I_O | C21| | | | R13 | I_O | C26| | | | R14 | I_O | C20| | | | R15 | I_O | C28| | | | R16 | I_O | D0 | | | | T1 | I_O | A28| | | | T2 | I_O | B5 | | | | T3 | I_O | B8 | | | | T4 | I_O | B10| | | | T5 | I_O | B12| | | | T6 | I_O | B18| | | | T7 | I_O | B20| | | | T8 | I_O | B26| | | | T9 | I_O | B28| | | | T10 | I_O | C2 | | | | T11 | I_O | C4 | | | | T12 | I_O | C5 | | | | T13 | I_O | C6 | | | | T14 | I_O | C8 | | | | T15 | I_O | C16| | | | T16 | I_O | C18| | | | ------------------------------------------------------------------- <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal ---------------------------------------- ---------------------------------------- Output_Signal_List
I C P R Output N L Mc R E C O I F Fanout Pin GLB P PTs S Type E S E E R P Pwr Slew Pullup Signal ---------------------------------------------------------------------- G16 E 0 0 1 COM -------- Hi Fast Up q ---------------------------------------------------------------------- <Note> Power : Hi = High Lo = Low <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms PRE = Has preset equation RES = Has reset equation CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used Bidir_Signal_List
I C P R Bidir N L Mc R E C O I F Fanout Pin GLB P PTs S Type E S E E R P Pwr Slew Pullup Signal ---------------------------------------------------------------------- ---------------------------------------------------------------------- <Note> Power : Hi = High Lo = Low <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms PRE = Has preset equation RES = Has reset equation CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used Buried_Signal_List
Signals_Fanout_List
Signal Source : Fanout List ------------------------------------------------------------ ------------------------------------------------------------ <Note> {.} : Indicates GLB location of signal GLB_E_CLUSTER_TABLE
CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC GGGGGBBB I L X C 0000 0000 0011 1111 1111 2222 2222 2233 CCORPCCA / P P P 0123 4567 8901 2345 6789 0123 4567 8901 KEEEEKER Type O T T T Signal ----------------------------------------------------------------------------- M00 *--- ---- ---- ---- ---- ---- ---- ---- -------- M01 -*-- ---- ---- ---- ---- ---- ---- ---- -------- M02 --*- ---- ---- ---- ---- ---- ---- ---- -------- M03 ---* ---- ---- ---- ---- ---- ---- ---- -------- M04 ---- *--- ---- ---- ---- ---- ---- ---- -------- M05 ---- -*-- ---- ---- ---- ---- ---- ---- -------- M06 ---- --*- ---- ---- ---- ---- ---- ---- -------- M07 ---- ---* ---- ---- ---- ---- ---- ---- -------- M08 ---- ---- *--- ---- ---- ---- ---- ---- -------- M09 ---- ---- -*-- ---- ---- ---- ---- ---- -------- M10 ---- ---- --*- ---- ---- ---- ---- ---- -------- M11 ---- ---- ---* ---- ---- ---- ---- ---- -------- M12 ---- ---- ---- *--- ---- ---- ---- ---- -------- M13 ---- ---- ---- -*-- ---- ---- ---- ---- -------- M14 ---- ---- ---- --*- ---- ---- ---- ---- -------- M15 ---- ---- ---- ---* ---- ---- ---- ---- -------- M16 ---- ---- ---- ---- *--- ---- ---- ---- -------- M17 ---- ---- ---- ---- -*-- ---- ---- ---- -------- M18 ---- ---- ---- ---- --*- ---- ---- ---- -------- M19 ---- ---- ---- ---- ---* ---- ---- ---- -------- M20 ---- ---- ---- ---- ---- *--- ---- ---- -------- M21 ---- ---- ---- ---- ---- -*-- ---- ---- -------- M22 ---- ---- ---- ---- ---- --*- ---- ---- -------- M23 ---- ---- ---- ---- ---- ---* ---- ---- -------- M24 ---- ---- ---- ---- ---- ---- *--- ---- -------- M25 ---- ---- ---- ---- ---- ---- -*-- ---- -------- M26 ---- ---- ---- ---- ---- ---- --*- ---- -------- M27 ---- ---- ---- ---- ---- ---- ---* ---- -------- M28 ---- ---- ---- ---- ---- ---- ---- *--- -------- M29 ---- ---- ---- ---- ---- ---- ---- -*-- -------- M30 ---- ---- ---- ---- ---- ---- ---- --0- -------- OUT 30 0 0 0 q M31 ---- ---- ---- ---- ---- ---- ---- ---* -------- ----------------------------------------------------------------------------- <Note> Pin clocks, block clocks, block resets, block presets and output enables are not included in the ctrl pterm counts in the above tables. <Note> LPT = Number of Logic Pterms XPT = Number of XOR Pterms CPT = Number of Control Pterms <Note> TPT = Number of Pterm Adders <Note> GCK = Global Pin Clock GCE = Global Pin Clock Enable GOE = Global Pin Output Enable GRE = Global Pin Reset GPE = Global Product Term Enable BCK = Block Asynchronous Clock BCE = Block Clock Enable BAR = Block Asynchronous Reset GLB_E_LOGIC_ARRAY_FANIN
GI Source Signal GI Source Signal ----------------------------- ----------------------------- 00 ... ... 34 ... ... 01 ... ... 35 ... ... 02 ... ... 36 ... ... 03 ... ... 37 ... ... 04 ... ... 38 ... ... 05 ... ... 39 ... ... 06 ... ... 40 ... ... 07 ... ... 41 ... ... 08 ... ... 42 ... ... 09 ... ... 43 ... ... 10 ... ... 44 ... ... 11 ... ... 45 ... ... 12 ... ... 46 ... ... 13 ... ... 47 ... ... 14 ... ... 48 ... ... 15 ... ... 49 ... ... 16 ... ... 50 ... ... 17 ... ... 51 ... ... 18 ... ... 52 ... ... 19 ... ... 53 ... ... 20 ... ... 54 ... ... 21 ... ... 55 ... ... 22 ... ... 56 ... ... 23 ... ... 57 ... ... 24 ... ... 58 ... ... 25 ... ... 59 ... ... 26 ... ... 60 ... ... 27 ... ... 61 ... ... 28 ... ... 62 ... ... 29 ... ... 63 ... ... 30 ... ... 64 ... ... 31 ... ... 65 ... ... 32 ... ... 66 ... ... 33 ... ... 67 ... ... -------------------------------------------------------------- <Note> GI indicates the GLB inputs into the AND array. <Note> Source indicates where the signal comes from (pin or macrocell). PostFit_Equations
------------------------ Product Term Histogram ------------------------ 0 pterms : 1 (1 ) ------------------------ <Note> The number of pterms in the above histogram counts only cluster pterms used. It does not include pterms from control equations placed on global pins or block level product terms. <Note> The value in brackets is the cumulative number of functions having less than or equal number of product terms. ------------------------ GLB Input Histogram ------------------------ 0 inputs : 1 (1 ) ------------------------ <Note> The number of block inputs in the above histogram counts only signal sources that are inputs to the AND array. It does not include signal sources assigned to global pins. <Note> The value in brackets is the cumulative number of functions having less than or equal number of signal sources. q = 1 ; (1 pterm, 0 signal)