[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Fwd: Re: congratulations / clock?]
Oops ... forgot to respond to Peter and Steve....
-------- Original Message --------
From: - Mon Jun 16 14:55:07 2003
X-Mozilla-Status: 0001
X-Mozilla-Status2: 00000000
Message-ID: <3EEE1276.8060906@bu.edu>
Date: Mon, 16 Jun 2003 14:54:46 -0400
From: Kevin Lynch <krlynch@bu.edu>
Reply-To: krlynch@bu.edu
Organization: Boston University Physics Department
User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.3) Gecko/20030312
X-Accept-Language: en-us, en
MIME-Version: 1.0
To: Fred Gray <fegray@socrates.berkeley.edu>
Subject: Re: congratulations / clock?
References: <20030616021405.GA17891@socrates.berkeley.edu>
<3EEDD324.6010800@bu.edu> <20030616172056.GB18777@socrates.berkeley.edu>
In-Reply-To: <20030616172056.GB18777@socrates.berkeley.edu>
Content-Type: text/plain; charset=us-ascii; format=flowed
Content-Transfer-Encoding: 7bit
Hi again, Fred
Here are a few more detailed questions ....
Fred Gray wrote:
> On Mon, Jun 16, 2003 at 10:24:36AM -0400, Kevin Lynch wrote:
>
> Hi, Kevin,
>
> I'm cc'ing this to Peter and Steve; hopefully they can correct me if I'm
> wrong here, though I think Peter is on vacation now. The frequencies that
> we need are:
>
> To be used for high-precision timing:
What do you mean by high-precision? Do you need the clock for timing
accuracy, as in MuLan, which will require the nominal frequency to match
the actual frequency to a few parts in, say, 10^6? Or do you just need
a very tightly constrained drift specification, that is, small
day-to-day or hour-to-hour frequency drift?
> - g-2 WFDs: 200 MHz sine wave
> * g-2 clock fanout box already being used
This shouldn't be a problem
> - ePC COMET compressors: 50 MHz, 50% duty cycle, NIM levels
> * fanned out by controller module
We can divide this down from the 200MHz sine wave with a high speed ECL
flip-flop based circuit ... conversion to NIM is probably best done with
a high speed NIM discriminator module, unless it is essential that that
50% duty cycle be dead on (that is, the compressors operate on both
clock edges....)
> - CAEN TDCs: 25 MHz, 50% duty cycle, ECL levels
> * three of these; can be daisy-chained
>
ECL is no problem ... but just so that we are on the same page: does the
device require ECL logic levels for the clock (-0.8V and -1.6V) or
signals compatible with ECL, but without the offset (0.8Vpp)? Again,
we'll divide this one down from the main 200MHz clock.
> Probably not to be used for high-precision timing:
> - TDC400s: 5 MHz, 50% duty cycle, ECL levels
> * seven of these; can be daisy-chained
This one is slightly more challenging, just because it is a factor of 40
smaller than the 200MHz clock. If this really doesn't need to be high
precision, we might be able to get away with a cheap crystal oscillator
signal that we convert to ECL. Same ECL level questions.
> - Struck flash ADCs: internal clock will be fine
>
This is the easiest one of all :-)
Final question: when is all this stuff needed at PSI?
--
-------------------------------------------------------------------------------
Kevin Lynch voice: (617) 353-6025
Physics Department Fax: (617) 353-9393
Boston University office: PRB-361
590 Commonwealth Ave. e-mail: krlynch@bu.edu
Boston, MA 02215 USA http://budoe.bu.edu/~krlynch
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
Kevin Lynch voice: (617) 353-6025
Physics Department Fax: (617) 353-9393
Boston University office: PRB-361
590 Commonwealth Ave. e-mail: krlynch@bu.edu
Boston, MA 02215 USA http://budoe.bu.edu/~krlynch
-------------------------------------------------------------------------------