Re: MuCap electronics cabinet

[Peter Kammel <kammel@npl.uiuc.edu>]

Dear Tom,


On Tue, 18 Mar 2003, Tom Banks wrote:

> 
> Hi Peter,
> 
> I'm currently at work on the CAENs, and I am trying to fix this damned
> clock business once and for all.  After studying the signals with the
> scope, I believe that the problem is most likely the NIM/ECL converter--
> the ECL output signal is absolutely horrendous and distorted, so the CAENs
> are not receiving the healthy 50% duty cycle signal they require.
> 
> Therefore, I would like to first attempt to swap modules, and see if that
> remedies the situation.  The problem is that I cannot get into either the
> electronics cabinet (on the landing above the muE4 area), or the lockbox
> just inside the door of our barrack, where I know that our keys are
> sometimes kept.  Do you know where any of these keys could be found?

You have to be careful how you look at the ECL signals, so that your
observation does not introduce the distortion.
Once you made some progress, we could talk on the phone one of these
days to discuss the technicalities. and possible solutions.


> 
> BTW, if the CAEN problems have been due to a faulty ECL signal, then it is
> likely that we could return the CAENs to a 50 MHz signal after all.  I
> will, of course, check that the CAENs operate properly at that rate, but
> the CAEN people seemed to think that 50 MHz would be fine.
> 

I would discourage the use of 50 MHz, always risky and no real reason to
run at the limit. BTW I dug up an old e-mail (1999) from one of the
responsible CAEN engineers (Guido Guidi).
----------------
We  received the speed graded IC we were waiting for beginning of June and
we tested the module at 60MHz clock using these new chip. The Tdc chip
itself  has a 40 MHz clock frequency limit in its specification  but, from
some tests that had done at Cern a long time ago on one single chip,
seemed to be possible to go up to 60; on the other hand in the V767 board
we have 4 Tdc chips that are read by a 'token ring' mode, and when reading
out the Tdc chips with no data inside at 60MHz rate problems among chips
came out at this level. 
Good results at 60MHz rate have been reached when using the 'Start Trigger
Matching' mode only. In fact the Stop Trigger Matching operational mode
showed the problems above mentioned due to the possible absence of data
inside the Tdc chips when read out at  60MHz;
The Continuous Storage and Start Gating modes have been cut off to make
the front-end controller reach the 60MHz rate.

Thus, concerning the 60MHz subject, I would like to know if:  

1. You are really  interested to this modification.
2. You can live with the Start Trigger Matching mode only.

And, most of all,  I would propose that you test one V767-60MHz in your
lab and, if it suits your experiment requirements we will product for you
the boards provided that you accept the features limitation due to the
modification itself.
---------------

> Tom
> 
> P.S.  I almost forgot--are any of our PSI bicycles still here?  I could
> really use one.
> 
The bicyles are in a large, open wooden shack in the south-east corner
behind the neutron area of the experimental hall. Mr Gnaedinger would
know.


Best regards

Peter